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1 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas inc. 2011. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners. 36v rad hard dual precision operational amplifier isl70227srh the isl70227srh is a high precision dual operational amplifier featuring very low noise, low offset voltage, low input bias current and low temperature drift. these features plus its radiation tolerance make the isl70227srh the ideal choice for applications requiring both high dc accuracy and ac performance. the combination of precision, low noise, and small footprint provides the user with outstanding value and flexibility relative to similar competitive parts. applications for these amplif iers include precision and analytical instrumentation, ac tive filters, precision power supply controls, and industrial controls. the isl70227srh is available in a 10 ld hermetic ceramic flatpack and operates over the extended temperature range of -55c to +125c. applications ? precision instruments ? industrial controls ? active filter blocks ? data acquisition ? power supply control features ? wide supply range . . . . . . . . . . . . . . . . . . . .4.5v to 36v max. ? very low voltage noise . . . . . . . . . . . . . . . . . .2.5nv/ hz, typ. ? gain-bandwidth product . . . . . . . . . . . . . . . . . . . . . . . . 10mhz ? superb offset drift . . . . . . . . . . . . . . . . . . . . . . . . 1v/c, max ? operating temperature range. . . . . . . . . . . . -55c to +125 ? low input voltage offset . . . . . . . . . . . . . . . . . . . . . . 10v, typ. ? input bias current . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1na, typ. ? unity gain stable ? no phase reversal ? radiation tolerance - high dose rate. . . . . . . . . . . . . . . . . . . . . . . . . . 100krad(si) - low dose rate . . . . . . . . . . . . . . . . . . . . . . . . . . 100krad(si) - sel/seb let th . . . . . . . . . . . . . . . . . . . . . . 86mev/mg/cm 2 related literature ? see an1669 , ?isl70227srh evaluation board user?s guide? - + output v + r 1 v - r 2 c 1 c 2 sallen-key low pass filter (1mhz) v in 95.3 232 68.3nf 1.5nf figure 1. typical application isl70227srh figure 2. offset voltage vs radiation -30 -25 -20 -15 -10 -5 0 0 102030405060708090100 v o s ( v ) total dose (krad(si)) grounded biased september 23, 2011 fn7925.1
isl70227srh 2 fn7925.1 september 23, 2011 . pin configuration ordering information ordering number part marking temp range (c) package (pb-free) pkg. dwg. # isl70227srhmf (notes 1, 2) isl70227 sr hmf -55 to +125 10 ld flatpack k10.a isl70227srhf/proto (notes 1, 2) isl70227 sr hf/proto -55 to +125 10 ld flatpack k10.a isl70227srhmx -55 to +125 die isl70227srhx/sample -55 to +125 die ISL70227MHEVAL1Z evaluation board notes: 1. these intersil pb-free hermetic packaged products employ 100% au plate - e4 termination finish, which is rohs compliant and c ompatible with both snpb and pb-free soldering operations. 2. for moisture sensitivity level (msl), please see device information page for isl70227srh . for more information on msl please see techbrief tb363 . isl70227srh (10 ld flatpack) top view pin descriptions pin number pin name equivalent circuit description 3 +in_a circuit 1 amplifier a non-inverting input 5 v- circuit 3 negative power supply 7 +in_b circuit 1 amplifier b non-inverting input 8 -in_b circuit 1 amplifier b inverting input 9 out b circuit 2 amplifier b output 10 v+ circuit 3 positive power supply 1 out a circuit 2 amplifier a output 2 -in_a circuit 1 amplifier a inverting input 4, 6 nc - not connected ? this pin is not electrically connected internally. 10 9 8 7 6 2 3 4 5 1 outa -in a +in a nc v- v+ out b -in b +in b nc + - + - v+ v- out circuit 2 circuit 1 v+ v- circuit 3 in- v+ v- in+ capacitively triggered esd clamp
isl70227srh 3 fn7925.1 september 23, 2011 absolute maximum ratings thermal information maximum supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36v maximum differential input current . . . . . . . . . . . . . . . . . . . . . . . . . . 20ma maximum differential input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.5v min/max input voltage . . . . . . . . . . . . . . . . . . . . . . . . v- - 0.5v to v+ + 0.5v max/min input current for input voltage >v+ or isl70227srh 4 fn7925.1 september 23, 2011 i s supply current/amplifier - 2.2 2.8 ma - - 3.7 ma i sc short-circuit r l = 0 ? to ground - 45 - ma v supply supply voltage range guaranteed by psrr 2.25 - 15 v ac specifications gbw gain bandwidth product - 10 - mhz e np-p voltage noise 0.1hz to 10hz - 85 - nv p-p e n voltage noise density f = 10hz - 3 - nv/ hz e n voltage noise density f = 100hz - 2.8 - nv/ hz e n voltage noise density f = 1khz - 2.5 - nv/ hz e n voltage noise density f = 10khz - 2.5 - nv/ hz in current noise density f = 10khz - 0.4 - pa/ hz thd + n total harmonic distortion + noise 1khz, g = 1, v o = 3.5v rms , r l = 2k ? - 0.00022 - % transient response sr slew rate a v = 10, r l = 2k ? , v o = 4v p-p - 3.6 - v/s t r , t f , small signal rise time 10% to 90% of v out a v = -1, v out = 100mv p-p , r f = r g = 2k ? , r l = 2k ? to v cm - 36 - ns fall time 90% to 10% of v out a v = -1, v out = 100mv p-p , r f = r g = 2k ? , r l = 2k ? to v cm - 38 - ns t s settling time to 0.1% 10v step; 10% to v out a v = -1, v out = 10v p-p , r g = r f = 10k, r l = 2k ? to v cm - 3.4 - s settling time to 0.01% 10v step; 10% to v out a v = -1, v out = 10v p-p , r l = 2k ? to v cm - 3.8 - s t ol output overload recovery time a v = 100, v in = 0.2v, r l = 2k ? to v cm - 1.7 - s electrical specifications v s 5v, v cm = 0, v o = 0v, t a = +25c, unless otherwise noted. boldface limits apply over the operating temperature range, -55c to +125c. parameter description conditions min (note 5) typ max (note 5) unit v os offset voltage - -10 - v tcv os offset voltage drift - .1 - v/ c i os input offset current - 1 - na i b input bias current -1- na cmrr common-mode rejection ratio v cm = -3v to +3v - 120 - db psrr power supply rejection ratio v s = 2.25v to 5v - 125 - db a vol open-loop gain v o = -3v to +3v r l = 10k ? to ground - 1500 - v/mv v oh output voltage high r l = 10k ? to ground - 3.65 - v r l = 2k ? to ground - 3.5 - electrical specifications v s 15v, v cm = 0, v o = 0v, r l = open, t a = +25c, unless otherwise noted. boldface limits apply over the operating temperature range, -55c to +125c, and over the radiat ion tolerance limit with exposure at a high dose rate. (contin ued) parameter description conditions min (note 5) typ max (note 5) unit
isl70227srh 5 fn7925.1 september 23, 2011 v ol output voltage low r l = 10k ? to ground - -3.65 - v r l = 2k ? to ground - -3.5 - i s supply current/amplifier - 2.2 - ma i sc short-circuit - 45 - ma ac specifications gbw gain bandwidth product - 10 - mhz thd + n total harmonic distortion + noise 1khz, g = 1, vo = 2.5v rms , r l = 2k ? - 0.0034 - % transient response sr slew rate a v = 10, r l = 2k ? oh - 3.6 - v/s t r , t f , small signal rise time 10% to 90% of v out a v = -1, v out = 100mv p-p , r f = r g = 2k ? , r l = 2k ? to v cm - 36 - ns fall time 90% to 10% of v out a v = -1, v out = 100mv p-p , r f = r g = 2k ? , r l = 2k ? to v cm - 38 - ns t s settling time to 0.1% a v = -1, v out = 4v p-p , r f = r g = 2k ? , r l = 2k ? to v cm - 1.6 - s settling time to 0.01% a v = -1, v out = 4v p-p , r f = r g = 2k ? , r l = 2k ? to v cm - 4.2 - s note: 5. compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. electrical specifications v s 5v, v cm = 0, v o = 0v, t a = +25c, unless otherwise noted. boldface limits apply over the operating temperature range, -55c to +125c. (continued) parameter description conditions min (note 5) typ max (note 5) unit post radiation characteristics v s 15v, v cm = 0v, v o = 0v, r l = open, t a = +25c, unless otherwise noted. this data is ate test data of the isl70227srh post radiation exposure at a high dose rate of 50 to 300rad(si)/s, these are not limits nor are they gu aranteed. parameter description conditions 50k rad 75k rad 100k rad unit v os offset voltage 34 30 30 v i os input offset current -1 -1 -2 na i b input bias current -1 -2 -3 na cmrr common-mode rejection ration v cm = -13v to +13v 155 155 155 db psrr power supply rejection ratio v s = 2.25v to 15v 116 116 116 db a vol open-loop gain v o = -13v to +13v r l = 10k ? to ground 3500 3500 3500 v/mv i s supply current/amplifier 2.2 2.2 2.2 ma
isl70227srh 6 fn7925.1 september 23, 2011 post radiation characteristics v s 15v, v cm = 0v, v o = 0v, r l = open, t a = +25c, unless otherwise noted. this data is ate test data of the isl70227srh post radiation exposure at a low dose rate of <10mrad(si)/s, these are not limits nor are t hey guaranteed. figure 3. offset voltage vs radiation figure 4. positive input bias current vs radiation figure 5. negative input bias current vs ra diation figure 6. offset current vs radiation figure 7. total supply current vs radiation -30 -25 -20 -15 -10 -5 0 0 102030405060708090100 v o s ( v ) total dose (krad(si)) grounded biased -5 0 5 10 15 0 102030405060708090100 total dose (krad(si)) i b + ( n a ) grounded biased -5 0 5 10 15 0 102030405060708090100 i b - ( n a ) total dose (krad(si)) grounded biased -5 0 5 0 102030405060708090100 total dose (krad(si)) i i o ( n a ) grounded biased 0 5 10 0 102030405060708090100 total dose (krad(si)) supply current (ma) grounded biased
isl70227srh 7 fn7925.1 september 23, 2011 typical performance curves v s = 15v, v cm = 0v, r l = open, unless otherwise specified. figure 8. input noise voltage 0.1hz to 10hz figure 9. input noise voltage spectral density figure 10. input noise current spectral density figure 11. psrr vs frequency, v s = 5v, 15v figure 12. cmrr vs frequency, v s = 2.25, 5v, 15v figure 13. v os vs temperature time (s) input noise voltage (nv) -60 -40 -20 0 20 60 80 100 012345678910 40 -80 -100 v + = 38v r l = 10k r g = 10, r f = 100k a v = 10,000 c l = 3.5pf frequency (hz) 1 10 100 0.1 1 10 100 1k 10k 100k v s = 19v a v = 1 input noise voltage (nv/ hz) frequency (hz) 1 10 100 input noise current (pa/ hz) 0.1 1 10 100 1k 10k 100k 0.1 v s = 19v a v = 1 0 psrr (db ) 100 1k 10k 100k 1m 10m frequency (hz) 10 20 40 60 80 100 120 -10 10 30 50 70 90 110 130 r l = inf a v = +1 v s = 1v p-p c l = 5.25pf psrr+ and psrr- v s = 15v psrr+ and psrr- v s = 5v 0 cmrr (db) 100 1k 10k 100k 1m 10m frequency (hz) 10 20 40 60 80 100 120 -10 10 30 50 70 90 110 130 r l = inf a v = +1 v cm = 1v p-p c l = 5.25pf v s = 15v v s = 2.25v v s = 5v 0 10 20 30 40 50 60 70 -60 -40 -20 0 20 40 60 80 100 120 140 v os (v) temperature (c) v s = 15v
isl70227srh 8 fn7925.1 september 23, 2011 figure 14. i b+ vs temperature figure 15. i b- vs temperature figure 16. i os vs temperature figure 17. supply current vs temperature figure 18. v oh vs temperature, v s = 15v figure 19. v ol vs temperature, v s = 15v typical performance curves v s = 15v, v cm = 0v, r l = open, unless otherwise specified. (continued) -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -60 -40 -20 0 20 40 60 80 100 120 140 i b+ (na) i b+ temperature (c) v s = 15v -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0 -60 -40 -20 0 20 40 60 80 100 120 140 i b- (na) i b- temperature (c) v s = 15v -1.4 -1.2 -1.0 -0.8 -0.6 -0.4 -0.2 0 -60 -40 -20 0 20 40 60 80 100 120 140 i io (na) i io temperature (c) v s = 15v 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 -60 -40 -20 0 20 40 60 80 100 120 140 i cc i cc (ma) temperature (c) v s = 15v 12.2 12.3 12.4 12.5 12.6 12.7 12.8 12.9 13.0 13.1 13.2 -60 -40 -20 0 20 40 60 80 100 120 v out (v) temperature (c) v oh @ r l = 100k v oh @ r l = 2k a v = 10, v in = 1.31v v s = 15v -13.2 -13.1 -13.0 -12.9 -12.8 -12.7 -12.6 -12.5 -12.4 -12.3 -12.2 -60 -40 -20 0 20 40 60 80 100 120 v out (v) temperature (c) v ol @ r l = 2k v ol @ r l = 100k a v = 10, v in = - 1.31v v s = 15v
isl70227srh 9 fn7925.1 september 23, 2011 figure 20. v oh vs output current figure 21. open-loop gain, phase vs frequency, r l =10k ? , c l = 10pf figure 22. v ol vs output current figure 23. open-loop gain, phase vs frequency, r l =10k ? , c l = 100pf figure 24. frequency response vs closed loop gain figure 25. gain vs frequency vs temperature typical performance curves v s = 15v, v cm = 0v, r l = open, unless otherwise specified. (continued) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 0.0001 0.001 0.01 0.1 1 10 v oh (v) output current (ma) v out (v) 0c v out (v) +25c v out (v) +125c v out (v) -55c a v = 10, v in = 1.31v v s = 15v open loop gain (db)/phase () frequency (hz) -100 -80 -60 -40 -20 0 20 40 60 80 100 120 140 160 180 200 0.1m 1m 10m 100m 1 10 100 1k 10k 100k 1m 10m 100m r l = 10k simulation c l = 10pf gain phase -14 -13 -12 -11 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 0.0001 0.001 0.01 0.1 1 10 v out (v) 0c v out (v) +25c v out (v) +125c v out (v) -55c v ol (v) output current (ma) a v = 10, v in = - 1.31v v s = 15v open loop gain (db)/phase() frequency (hz) -100 -80 -60 -40 -20 0 20 40 60 80 100 120 140 160 180 200 0.1m 1m 10m 100m 1 10 100 1k 10k 100k 1m 10m 100m r l = 10k simulation c l = 100pf gain phase frequency (hz) gain (db) 100k 1m 10m 100m 10k 1k -10 0 10 20 30 40 50 60 70 100 a v = 1 a v = 100 a v = 1000 v s = 15v v out = 100mv p-p c l = 3.5pf r l = inf r g = 100, r f = 100k r g = 10k, r f = 100k a v = 10 r g = 1k, r f = 100k r g = open, r f = 0 11 12 13 14 15 16 17 18 19 20 21 100 1k 10k 100k 1m 10m frequency (hz) gain (db) a v = 10, v out = 100mv p-p , v s = +-15v, r l = 2k ? +25c -60c +125c +130c
isl70227srh 10 fn7925.1 september 23, 2011 figure 26. frequency response vs feedback resistance r f /r g figure 27. gain vs frequency vs r l figure 28. gain vs frequency vs c l figure 29. gain vs frequency vs supply voltage figure 30. large signal 10v step response, v s = 15v figure 31. large signal 10v step response, v s = 15v vs temperature typical performance curves v s = 15v, v cm = 0v, r l = open, unless otherwise specified. (continued) normalized gain (db) -5 -3 -1 1 3 5 7 9 11 13 15 frequency (hz) 100k 1m 10m 100m 10k 1k r f = r g = 100k r f = r g = 100 r f = r g = 10k r f = r g = 1k v s = 15v r l = 10k a v = +2 v out = 100mv p-p c l = 3.5pf -5 -4 -3 -2 -1 0 1 2 frequency (hz) normalized gain (db) 100k 1m 10m 100m 10k 1k v s = 15v a v = +1 v out = 100mv p-p c l = 3.5pf r l = 100 r l = 49.9 r l = 10k r l = 1k r l = 499 normalized gain (db) frequency (hz) 100k 1m 10m 100m 10k 1k -3 -2 -1 0 1 2 3 4 5 6 7 v s = 15v r l = 10k a v = +1 v out = 100mv p-p c l = 1000pf c l = 220pf c l = 100pf c l = 25.5pf c l = 3.5pf normalized gain (db) frequency (hz) 100k 1m 10m 100m 10k 1k -3 -2 -1 0 1 c l = 3.5pf r l = 10k a v = +1 v out = 100mv p-p v s = 2.25v v s = 5v v s = 15v -6 -5 -4 -3 -2 1 0 1 2 3 4 5 6 0 5 10 15 20 25 30 time (s) large signal (v) v s = 15v a v = 1 c l = 3.5pf v out = 10v p-p r f = 0 r g = inf r l = 2k r l = 10k -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 0 10203040 large signal (v) time (s) output -55c output +125c output +25c v s = 15v a v = 1 r l = 2k v out = 10v p-p r f = 0 r g = inf
isl70227srh 11 fn7925.1 september 23, 2011 figure 32. large signal tr ansient response vs r l , v s = 5v, 15v figure 33. small signal transient response, v s = 5v, 15v figure 34. positive output overload response time, v s = 15v figure 35. negative output overload response time, v s =15v figure 36. % overshoot vs load capacitance, v s = 15v typical performance curves v s = 15v, v cm = 0v, r l = open, unless otherwise specified. (continued) time (s) large signal (v) -2.4 -2.0 -1.6 -1.2 -0.8 -0.4 0 0.4 0.8 1.2 1.6 2.0 2.4 0 5 10 15 20 25 30 35 40 a v = 1 c l = 3.5pf v out = 4v p-p v s = 15v, r l = 2k, 10k v s = 5v, r l = 2k, 10k 80 60 40 20 0 20 40 60 80 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 time (ms) small signal (mv) r l = 2k a v = 1 c l = 3.5pf v out = 100mv p-p v s = 5v , 15v time (s) -0.26 -0.20 -0.18 -0.14 -0.10 -0.06 -0.02 0.02 0.06 0 5 10 15 20 25 30 35 40 -1 1 3 5 7 9 11 13 15 output (v) input (v) input output v s = 15v r l = 10k a v = 100 c l = 3.5pf r f = 100k, r g = 1k v in = 200mv p-p time (s) -0.06 -0.02 0.02 0.06 0.10 0.04 0.08 0.22 0.26 0 5 10 15 20 25 30 35 40 -14 -12 -10 -8 -6 -4 -2 0 2 output (v) input (v) input output v s = 15v r l = 10k a v = 100 c l = 3.5pf r f = 100k, r g = 1k v in = 200mv p-p capacitance (pf) 0 10 20 30 40 50 60 70 80 90 10 100 1000 10000 o v e r s h o o t + v s = 15v r l = 10k a v = 1 v out = 100mv p-p o v e r s h o o t - overshoot (%)
isl70227srh 12 fn7925.1 september 23, 2011 applications information functional description the isl70227srh is a dual, low noise 10mhz bw precision op amp fabricated in a new precision 40v complementary bipolar di process. a super-beta npn input stage with input bias current cancellation provides low input bias current (1na typical), low input offset voltage (10v typ), low input noise voltage (3nv/ hz), and low 1/f noise corner frequency (5hz). these amplifiers also feature high open loop gain (1500v/mv) for excellent cmrr (120db) and thd+n performance (0.0002% @ 3.5v rms , 1khz into 2k ? ). a complimentary bipolar output stage enables high capacitive load drive without external compensation. operating voltage range the devices are designed to operate over the 4.5v (2.25v) to 36v (18v) range and are fully characterized at 30v (15v). parameter variation with operat ing voltage is shown in the ?typical performance curv es? beginning on page 7. input esd diode protection the input terminals (in+ and in-) have internal esd protection diodes to the positive and negative supply rails, and an additional anti-parallel diode pair across the inputs (see figures 37 and 38). for unity gain applications (see figure 37) where the output is connected directly to the non-inverting input a current limiting resistor (r in ) will be needed under the following conditions to protect the anti-parallel differential input protection diodes. ? the amplifier input is supplied from a low impedance source. ? the input voltage rate-of-rise (dv/dt) exceeds the maximum slew rate of the am plifier (3.6v/s). if the output lags far enough be hind the input, the anti-parallel input diodes can conduct. for ex ample, if an input pulse ramps from 0v to +10v in 1s, then the output of the isl70227srh will reach only +3.6v (slew rate = 3.6v/s) while the input is at 10v, the input differential voltage of 6.4v will force input esd diodes to conduct, dumping the input current directly into the output stage and the load. the resulting current flow can cause permanent damage to the esd diodes. the esd diodes are rated to 20ma, and in the previous example, setting r in to 1k resistor (see figure 37) would limit the current to <6.4ma, and provide additional protection up to 20v at the input. in applications where one or both amplifier input terminals are at risk of exposure to high voltage, current limiting resistors may be needed at each input terminal (see figure 38 r in +, r in -) to limit current through the power supply esd diodes to 20ma. output current limiting the output current is internally limited to approximately 45ma at +25c and can withstand a short circuit to either rail as long as the power dissipation limits are not exceeded. this applies to only 1 amplifier at a time. co ntinuous operation under these conditions may degrade long term reliability. output phase reversal output phase reversal is a change of polarity in the amplifier transfer function when the input voltage exceeds the supply voltage. the isl70227srh are immune to output phase reversal, even when the input voltage is 1v beyond the supplies. power dissipation it is possible to exceed the +150c maximum junction temperatures under certain load and power supply conditions. it is therefore important to ca lculate the maximum junction temperature (t jmax ) for all applications to determine if power supply voltages, load conditions, or package type need to be modified to remain in the safe operating area. these parameters are related using equation 1: where: ?p dmaxtotal is the sum of the maximum power dissipation of each amplifier in the package (pd max ) ?pd max for each amplifier can be calculated using equation 2: where: ?t max = maximum ambient temperature ? ja = thermal resistance of the package ?pd max = maximum power dissipation of 1 amplifier ?v s = total supply voltage ?i qmax = maximum quiescent supply current of 1 amplifier ?v outmax = maximum output voltage swing of the application ?r l = load resistance figure 37. input esd diode current limiting - unity gain - + r in r l v in v out v+ v- figure 38. input esd diode current limiting - differential input - + r in - r l v in - v out v+ v- r in + v in + t jmax t max ja xpd maxtotal + = (eq. 1) pd max v s i qmax v s ( - v outmax ) v outmax r l ------------------------ + = (eq. 2)
isl70227srh 13 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn7925.1 september 23, 2011 for additional products, see www.intersil.com/product_tree products intersil corporation is a leader in the design and manufacture of high-performance analog semico nductors. the company's product s address some of the industry's fastest growing markets, such as , flat panel displays, cell phones, handheld products, and noteb ooks. intersil's product families address power management and analog signal processing functions. go to www.intersil.com/products for a complete list of intersil product families. for a complete listing of applications, rela ted documentation and related parts, please see the respective device information p age on intersil.com: isl70227srh to report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff fits are available from our website at: http://rel.intersil.co m/reports/search.php revision history the revision history provided is for informational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest rev. revision date change fn7925.1 9/20/11 added ?related literature? on page 1. made correction to ordering information - eval board name changed from "isl70227srheval1z" to "ISL70227MHEVAL1Z" fn7925.0 9/7/11 initial release.
isl70227srh 14 fn7925.1 september 23, 2011 ceramic metal seal fl atpack packages (flatpack) notes: 1. index area: a notch or a pin one identification mark shall be locat- ed adjacent to pin one and shall be located within the shaded area shown. the manufacturer?s identification shall not be used as a pin one identification mark. alternately, a tab (dimension k) may be used to identify pin one. 2. if a pin one identification mark is used in addition to a tab, the lim- its of dimension k do not apply. 3. this dimension allows for off- center lid, meniscus, and glass overrun. 4. dimensions b1 and c1 apply to lead base metal only. dimension m applies to lead plating and finish thickness. the maximum lim- its of lead dimensions b and c or m shall be measured at the cen- troid of the finished lead surfac es, when solder dip or tin plate lead finish is applied. 5. n is the maximum number of terminal positions. 6. measure dimension s1 at all four corners. 7. for bottom-brazed lead packages, no organic or polymeric mate- rials shall be molded to the bottom of the package to cover the leads. 8. dimension q shall be measured at the point of exit (beyond the meniscus) of the lead from t he body. dimension q minimum shall be reduced by 0.0015 inch (0.038mm) maximum when sol- der dip lead finish is applied. 9. dimensioning and tolerancing per ansi y14.5m - 1982. 10. controlling dimension: inch. -d- -c- 0.004 h a - b m d s s -a- -b- 0.036 h a - b m d s s e e a q l a e1 seating and l e2 e3 e3 base plane -h- b c s1 m c1 b1 (c) (b) section a-a base lead finish metal pin no. 1 id area a m d k10.a mil-std-1835 cdfp3-f10 (f-4a, configuration b) 10 lead ceramic metal seal flatpack package symbol inches millimeters notes min max min max a 0.045 0.115 1.14 2.92 - b 0.015 0.022 0.38 0.56 - b1 0.015 0.019 0.38 0.48 - c 0.004 0.009 0.10 0.23 - c1 0.004 0.006 0.10 0.15 - d - 0.290 - 7.37 3 e 0.240 0.260 6.10 6.60 - e1 -0.280-7.11 3 e2 0.125 - 3.18 - - e3 0.030 - 0.76 - 7 e 0.050 bsc 1.27 bsc - k 0.008 0.015 0.20 0.38 2 l 0.250 0.370 6.35 9.40 - q 0.026 0.045 0.66 1.14 8 s1 0.005 - 0.13 - 6 m - 0.0015 - 0.04 - n10 10- rev. 0 3/07

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